user?s guide nhd-0216sz- nsw-bbw-3v lcm (liquid crystal display module) rohs compliant for product support, contact newhaven display international, llc 2511 technology drive, #101 elgin, il 60124 tel: (847) 844-8795 fax: (847) 844-8796 november 7 , 200 8 newhaven display 2 lines x 16 characters version line transmissive side white led b/l stn-(negative) blue 6:00 view wide temperature (-20 ~ +70c) nhd- 0216- sz- n - sw- b - b- w- 3v- 3 volt
nhd-0216sz- nsw - bbw-3v spe c ifi c at i ons of lcd module features 1. 5x8 dots with cursor 2. built-in controller (splc780d) 3. +3.0v power supply 4. 1/16 duty cycle 5. s tn-blue / negative display mode 6. le d s ide -light (white) 7. bkl to be driven by pin15, pin16 8. viewing angle: 6 o clock outline dimension display pattern le d bkl without bkl el bkl or absolute maximum ratings item symbol standard unit power voltage v dd -v ss 0 - 7.0 input voltage vin vss - vdd v operating temperature range vop -20 - +70 storage temperature range vst -30 - +80 * wide temperature range is available newhaven display international, llc 1/9 14 1 15 16
nhd-0216sz- n sw- b bw -3v newhaven display international, llc 2/9 block diagram seg1~40 8 db0~db7 vdd vss v0 r/w rs e controller driver and lcd com1~16 seg. led side bkl driver seg41~120 lcd panel 51 interface pin description pin no. symbol external connection function 1 v ss signal ground for lcm (gnd) 2 v dd power supply for logic (+3v) for lcm 3 v 0 power supply contrast adjust 4 rs mpu register select signal 5 r/w mpu read/write select signal 6 e mpu operation (data read/write) enable signal 7~10 db0~db3 mpu four low order bi-directional three-state data bus lines. used for data transfer between the mpu and the lcm. these four are not used during 4-bit operation. 11~14 db4~db7 mpu four high order bi-directional three-state data bus lines. used for data transfer between the mpu 15 led+ power supply for bkl (+3.0v) 16 led- led bkl power supply power supply for bkl (gnd) contrast adjust v dd~ v 0 : lcd driving voltage vr: 10k~20k backlight circuit diagram led ratings(white) (voltage=5v,r=51 ) item symbol min typ. max unit forward voltage vf - 3.0 - v forward current if 36 ma power p 180 mw peak wave length p nm luminance lv cd/m2
NHD-0216SZ-NSW-BBW-3V newhaven display international, llc 3/9 optical characteristics fstn type display module (ta=25 , vdd=5.0v) item symbol condition min. typ. max. unit 70 - viewing angle c r 4 -90 - 90 deg contrast ratio c r - 4 - - response time (rise) t r - - 150 - response time (fall) t r - - 250 - ms stn type display module (ta=25 , vdd=5.0v) item symbol condition min. typ. max. unit -60 - 35 viewing angle c r 2 -40 -40 deg contrast ratio c r - 6 - - response time (rise) t r - - 150 250 response time (fall) t r - - 150 250 ms electrical characteristics dc characteristics parameter symbol conditions min. typ. max. unit supply voltage for lcd v dd -v 0 ta =25 - 3.0 - input voltage v dd 4.7 - 5.5 v supply current i dd ta=25 , v dd =3.0v - 1.5 2.0 ma input leakage current i lkg - - 1.0 ua h level input voltage v ih 2.2 - v dd l level input voltage v il twice initial value or less 0 - 0.6 h level output voltage v oh loh=-0.25ma 2.4 - - l level output voltage v ol loh=1.6ma - - 0.4 backlight supply voltage v f - 3.0 - v backlight current if v f =3.0v -36- ma read cycle (ta=25 , vdd=5.0v) parameter symbol te st p i n min. typ. max. unit enable cycle time t c 1000 - - enable pulse width t w 450 - - enable rise/fall time t r, t f e - - 25 rs; r/w setup time t su 60 - - rs; r/w address hold time t h rs; r/w rs; r/w 20 - - read data output delay t d - - 360 read data hold time t dh db0~db7 5- - ns write cycle (ta=25 , vdd=5.0v) parameter symbol te st p i n min. typ. max. unit enable cycle time t c 1000 - - enable pulse width t w 450 - - enable rise/fall time t r, t f e - - 25 rs; r/w setup time t su1 60 - - rs; r/w address hold time t h1 rs; r/w rs; r/w 20 - - read data output delay t su2 195 - - read data hold time t h2 db0~db7 10 - - ns
NHD-0216SZ-NSW-BBW-3V newhaven display international, llc 4/9 write mode timing diagram read mode timing diagram instruction description outline to overcome the speed difference between the internal clock of splc780d and the mpu clock, splc780d performs internal operations by storing control in formations to ir or dr. the internal operation is determined according to the signal from mpu, composed of read/write and data bus (refer to table7). instructions can be divided largely into four groups: 1) splc780d function set instructions (set display methods, set data length, etc.) 2) address set instructions to internal ram 3) data transfer instructions with internal ram 4) others the address of the internal ram is automatically increased or decreased by 1. note: during internal operation, busy flag (db7) is read high . busy flag check must be preceded by the next instruction.
NHD-0216SZ-NSW-BBW-3V newhaven display international, llc 5/9 instruction table instruction code instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 description execution time (fosc= 270 khz clear display 0 0 0 0 0 0 0 0 0 1 write 20h to ddra and set ddram address to 00h from ac 1.53ms return home 0 0 0 0 0 0 0 0 1 - set ddram address to 00h from ac and return cursor to its original position if shifted. the contents of ddram are not changed. 1.53ms entry mode set 0 0 0 0 0 0 0 1 i/d sh assign cursor moving direction and blinking of entire display 39us display on/ off control 0 0 0 0 0 0 1 d c b set display (d), cursor (c), and blinking of cursor (b) on/off control bit. cursor or display shift 0 0 0 0 0 1 s/c r/l - - set cursor moving and display shift control bit, and the direction, without changing of ddram data. 39us function set 0 0 0 0 1 dl n f - - set interface data length (dl: 8- bit/4-bit), numbers of display line (n: =2-line/1-line) and, display font type (f: 5x11/5x8) 39us set cgram address 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 39us set ddram address 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 39us read busy flag and address 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 whether during internal operation or not can be known by reading bf. the contents of address counter can also be read. 0us write data to address 1 0 d7d6d5d4d3d2d1d0 write data into internal ram (ddram/cgram). 43us read data from ram 1 1 d7d6d5d4d3d2d1d0 read data from internal ram (ddram/cgram). 43us note: when an mpu program with checking the busy flag (db7) is made, it must be necessary 1/2fosc is necessary for executing the next instruction by the falling edge of the e signal after the busy flag (db7) goes to low . contents 1) clear display rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 1 clear all the display data by writing 20h (space code) to all ddram address, and set ddram address to 00h into ac (address counter). return cursor to the original status, namely, bring the cursor to the left edge on the fist line of the display. make the entry mode increment (i/d= high ).
NHD-0216SZ-NSW-BBW-3V newhaven display international, llc 6/9 2) return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 - return home is cursor return home instruction. set ddram address to 00h into the address counter. return cursor to its original site and return display to its original status, if shifted. contents of ddram does not change. 3) entry mode set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 i/d sh set the moving direction of cursor and display. i/d: increment / decrement of ddram address (cursor or blink) when i/d= high , cursor/blink moves to right and ddram address is increased by 1. when i/d= low , cursor/blink moves to left and ddram address is increased by 1. *cgram operates the same way as ddram, when reading from or writing to cgram. sh: shift of entire display when ddram read (cgram read/write) operation or sh= low , shifting of entire display is not performed. if sh = high and ddram write operation, shift of entire display is performed according to i/d value. (i/d= high . shift left, i/d= low . shift right). 4) display on/off control rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 d c b control display/cursor/blink on/off 1 bit register. d: display on/off control bit when d= high , entire display is turned on. when d= low , display is turned off, but display data remains in ddram. c: cursor on/off control bit when d= high , cursor is turned on. when d= low , cursor is disappeared in current display, but i/d register preserves its data. b: cursor blink on/off control bit when b= high , cursor blink is on, which performs alternately between all the high data and display characters at the cursor position. when b= low , blink is off. 5) cursor or display shift rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 s/c r/l - -
NHD-0216SZ-NSW-BBW-3V newhaven display international, llc 7/9 shifting of right/left cursor position or display without writing or reading of display data. thisinstructionisusedtocorrectorsearchdisplaydata. during2-linemodedisplay,cursormovestothe2ndlineafterthe40thdigitofthe1stline. note that display shift is performed simultaneously in all the lines. when display data is shifted repeatedly, each line is shifted individually. when display shift is performed, the contents of the address counter are not changed. shift patterns according to s/c and r/l bits s/c r/l operation 0 0 shift cursor to the left, ac is decreased by 1 0 1 shift cursor to the right, ac is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display 6) function set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n f - - dl: interface data length control bit when dl= high , it means 8-bit bus mode with mpu. when dl= low , it means 4-bit bus mode with mpu. hence, dl is a signal to select 8-bit or 4-bit bus mode. when 4-but bus mode, it needs to transfer 4-bit data twice. n: display line number control bit when n= low , 1-line display mode is set. when n= high , 2-line display mode is set. f: display line number control bit when f= low , 5x8 dots format display mode is set. when f= high , 5x11 dots format display mode. 7) set cgram address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address to ac. the instruction makes cgram data available from mpu. 8) set ddram address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address to ac. this instruction makes ddram data available form mpu. when 1-line display mode (n=low), ddram address is form 00h to 4fh .in 2-line display mode (n=high), ddram address in the 1st line form 00h to 27h , and ddram address in the 2nd line is from 40h to 67h .
NHD-0216SZ-NSW-BBW-3V newhaven display international, llc 8/9 9) read busy flag & addres s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 this instruction shows whether splc780d is in internal operation or not. if the resultant bf is high , internal operation is in progress and should wait bf is to be low, which by then the nest instruction can be performed. in this instruction you can also read the value of the address counter. 10) write data to ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write binary 8-bit data to ddram/cgram. the selection of ram from ddram, and cgram, is set by the previous address set instruction (ddram address set, c gram address set). ram set instruction can also determine the ac direction to ram. after write operation. the address is automatically increased/decreased by 1, according to the entry mode. 11) read data from ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read binary 8-bit data from ddram/cgram. the selection of ram is set by the previous address set instruction. if the address set instruction of ram is not performed before this instruction, the data that has been read first is invalid, as the direction of ac is not yet determined. if ram data is read several times without ram address instructions set before, read operation, the correct ram data can be obtained from the second. but the first data would be incorrect, as there is no time margin to transfer ram data. in case of ddram read operation, cursor shift instruction plays the same role as ddram address set instruction, it also transfers ram data to output data register. after read operation, address counter is automatically increased/decreased by 1 according to the entry mode. after cgram read operation, display shift may not be executed correctly. note: in case of ram write operation, ac is increased/decreased by 1 as in read operation. at this time, ac indicates next address position, but only the previous data can be read by the read instruction. display character address code: display position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ddram address 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ddram address 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f
NHD-0216SZ-NSW-BBW-3V newhaven display international, llc 9/9 standard character pattern
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